1. Field of the Invention
The present disclosure relates to a semiconductor device and a fabricating method thereof and, more particularly, to nano-scale MOS transistors with virtual source/drain extension areas and a fabricating method thereof.
2. Background of the Related Art
A conventional ion implantation method for forming a source/drain area has several shortcomings. One of these shortcomings is that implanted impurity ions can be diffused into a channel area by a later thermal treatment. Due to such a shortcoming, if the length of a gate electrode is equal to or less than 0.06 μm, a source area and a drain area may be easily connected through impurities, therefore preventing the fabrication of a MOS transistor. Even if the length of the gate electrode is more than 0.06 μm, a short channel effect may seriously occur because the shallow depth of the source/drain area is hardly formed to be less than 10 nm. Thus, to make a nano-scale transistor (i.e., below 0.1 μm) with a source/drain extension area, a virtual source/drain extension structure employing sidewall gate electrodes is drawing attention as one of alternatives.
FIG. 1 is a cross-sectional view illustrating a structure of the MOS transistor having three gate electrodes according to “Threshold voltage controlled 0.1 MOSFET utilizing inversion layer as extreme shallow source/drain.”, H. Noda et al., IEDM Tech. Dig., pages 123 to 126, published in 1993.
Referring to FIG. 1, an NMOS transistor comprises a main gate oxide layer 14 on a P-type silicon substrate 11, a polysilicon main gate electrode 17, an oxide layer 16, a gate oxide layer 15, a source area 12 and a drain area 13, and sidewall gates 18. The polysilicon main gate electrode 17 and sidewall gates 18 adjacent to the main gate electrode 17 are doped with a high concentration of N-type impurity ions.
The oxide layer 16 for insulation is formed between the gate electrode 17 and the sidewall gates 18. The gate oxide layer 15 is positioned between the sidewall gates 18 and the P-type silicon substrate 11.
When a constant voltage is applied to the sidewall gates 18, inversion layers are generated under the sidewall gates 18. The inversion layers function as source/drain extension areas in a MOS transistor. Therefore, when a voltage is applied to the main gate electrode 17, a channel will be created and current then flows between the source 12 and the drain 13.
If highly concentrated N+ ions are implanted in the polysilicon gate electrode, the difference of the work function may be about −1.0V, and the Fermi potential may be fixed between 0.4V and 0.45V. Thus, to control a threshold voltage, two methods are typically employed. One method is to adjust the amount of electric charges in a depletion area by tuning the concentration of a silicon substrate. The other is to implant N-type or P-type impurity ions into the silicon substrate.
For example, if the dopant concentration of the substrate is 1.0×1017 ions/cm3, a highly doped N+ polysilicon gate is used, the thickness of the gate oxide layer is approximately 50 Å, and no impurity ion is implanted into the surface of the substrate, the threshold voltage of a long channel transistor may be about 0.1V, and the threshold voltage of the short channel transistor may be less than 0.1V. Therefore, if a much higher voltage (e.g., 2V to 3V) than the threshold voltage is applied to the sidewall gates, a sufficient amount or depth of the inversion layers below the sidewall floating gates will be created to form source/drain extension areas.
Under the above-mentioned condition, the threshold voltage can be increased by implanting P-type impurity ions into the surface of the substrate and decreased by implanting N-type impurity ions into the surface of the substrate. Once they are implanted, the impurity ions may be diffused by a later thermal treatment. Moreover, even if the N-type impurity ions are implanted into the surface of the substrate, the threshold voltage may not fall below −1 to −2V. Therefore, a voltage has to be applied to the sidewall gates to create the virtual source/drain extension area.
However, applying a constant voltage to the sidewall gates has several problems, in that: (1) a contact should be formed on the sidewall gates; (2) the implanted ions for controlling the threshold voltage of the sidewall gates may be diffused by a later thermal treatment and affect the threshold voltage of the main gate electrode; (3) parasitic capacitance may be generated between the sidewall gates and the main gate electrode, between the sidewall gates and a body, and between the sidewall gates and the source/drain area, thereby decreasing propagation velocity of the voltage applied to the sidewall gates and thus degrading the characteristics of the transistor; (4) because a constant voltage should continue to be applied to the sidewall gates, additional leakage current may be generated, leading to an increase in power consumption; and (5) an insulating layer between the sidewall gates and the main gate electrode may deteriorate.
U.S. Pat. No. 4,698,787, to Mukherjee et al., discloses an electrically erasable programmable memory device which is programmable in the manner of an EPROM and erasable in the manner of an EEPROM. A dielectric layer between the control gate and the floating gate having a high dielectric constant is provided. A thin, uniform gate dielectric layer which demonstrates minimal trapping is provided.
U.S. Pat. No. 5,358,885, to Oku et al., discloses a method of producing a field effect transistor which can reduce the space between the over-hanging portion of a T-shaped gate electrode and the source electrode and increases the gate-to-source capacitance.
U.S. Pat. No. 6,329,248, to Yang et al., discloses a process for making split-gate semiconductor flash memory which contains an outwardly-diverging control gate stacked on, but separated from, a pair of opposing floating gates via an interpoly dielectric layer. The split-gate flash memory eliminates the over-erase problem experienced with the self-aligned ETOX flash memory cells, while allowing its cell dimension to be maintained, using the conventional photolithography technique.